1. Field of the Invention
The present invention relates to electronic devices, and in particular, to errors in electronic devices.
2. Description of Related Art
Radiation-induced transient errors in digital systems are often referred to as single event upsets (SEUs) or soft errors. Soft errors are mainly caused by radiation due to neutrons generated by cosmic rays from deep space and alpha particles from packaging material. Traditionally, soft errors are a major cause of concern mainly for space applications. However, for designs manufactured at technology nodes 130 nm and below, soft errors are gaining in importance even for terrestrial applications. Examples include processors and networking equipments targeted for high RAS (Reliability, Availability and Serviceability) applications. A major reason for increased significance of soft errors is the increased number of transistors inside an integrated circuit chip. Soft error rates of individual circuit blocks (e.g., memory cells) have not significantly increased over technology generations; however, an increased number of transistors inside a single chip results in increased chip level error rate. In addition to these soft errors, errors are generated in latches due to general noise and amplifier errors.
Corrupted latches and flip-flops may lead to incorrect machine states resulting in silent data corruption or system crash depending on where and when the error occurred. For example, errors in datapath latches or flip-flops may lead to silent data corruption if the errors are left undetected.
Conventional techniques such as error detection and correction are routinely employed to cope with soft errors in memories. The most usual concurrent error detection technique is to duplicate and compare. Other conventional techniques for soft error resilience of digital circuits include using radiation hardened materials and special circuit design techniques. In addition, many techniques developed in the context of fault-tolerant computing are also applicable. Most of these techniques either may require very sophisticated circuit design, architectural changes, changes in the software code and incur significant area, power or performance penalties or may be applicable to special designs such as for microprocessors.
While scan and other Design-For-Testability (DFT) mechanisms address manufacturing tests, they are not used in normal operation in the field. In scan cells, well-known sequential-test problems may be avoided by turning flip-flops (sometimes referred to as bistable devices, registers and master-slave latches) of a Device-Under-Test (DUT) at input and output nodes of combinational logic circuits into externally loadable and readable elements. During a test mode, these flip-flops are chained together as a single serial shift register to form a scan path. With respect to a given combinational logic circuit, serial data of an appropriate test pattern (vector) is loaded into flip-flops at an input node to set it to a predetermined state. The combinational logic circuit then functions in a normal manner, with the test pattern propagating through the logic circuit. The system response to the test pattern is latched by flip-flops at an output node and then are shifted out of the DUT in a scan-out operation and analyzed for improper operation.
Referring to FIG. 1, one conventional hold scan cell 10 is shown which is used for DFT purposes. The hold scan cell 10 provides a full shadow of the machine state and enables non-intrusive operation while the chip (not shown) is running or while the system clocks are frozen. Several versions of these types of scan cells exist and FIG. 1 illustrates only one type. The scan cell 10 includes a first flip-flop 12 (also referred to as a master-slave latch, register or bistable device) having a first datapath latch L1 and a second datapath latch L2 interposed in a datapath to receive DATA and clocks CLK1 and CLK2 (which may be two phases of a system clock) and to provide an output Q. The cell 10 further includes a second flip-flop 14 having a first shadow latch L3 and a second shadow latch L4. The scan cell 10 has two modes of operation: a normal or functional mode and a test mode. During the normal mode, clocks ACLK and BCLK and a signal Load are set at a logic value 0, and clocks CLK1 and CLK2 are applied. During the test mode, at a first scan cell 10 at an input node, clocks ACLK and BCLK are applied alternately to shift in (scan in) a test pattern or scan-in signal SI into shadow latches L3 and L4. Next, the store enable clock STORE_EN is applied to move the contents of latch L4 to latch L2 so that the test pattern has been written into the first flip-flop 12 and then applied in the normal fashion to a combinational logic circuit (not shown). A second cell 10 receives the system response to the test pattern from the logic circuit. The clock CLK1 of the second cell 10 is applied which captures or latches the system response in the latch L1, followed by applying the clock CLK2 which moves the latched contents of the latch L1 to the latch L2. Finally, the Load signal is applied which moves the contents of latch L2 into latch L3. The system response or scan-out signal SO may now be scanned out by alternately applying clocks ACLK and BCLK.